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Micrel, Inc.
Transceiver Sync/Non-Synchronous Mode
MICRF600/MICRF600Z
A6..A0
0000000
D7
LNA_by
D6
PA2
D5
PA1
D4
PA0
D3
Sync_en
D2
Mode1
D1
Mode0
D0
’1’
0000110
-
‘0’
‘0’
‘0’
BitSync_clkS2 BitSync_clkS1 BitSync_clkS0 BitRate_clkS2
0000111
BitRate_clkS1 BitRate_clkS0
RefClk_K5
RefClk_K4
RefClk_K3
RefClk_K2
RefClk_K1
RefClk_K0
Sync_en
0
0
1
1
State
Rx: Bit
synchronization off
Tx: DataClk pin off
Rx: Bit
synchronization on
Tx: DataClk pin on
Comments
Transparent reception of data
Transparent transmission of
data
Bit-clock is generated by
transceiver
Bit-clock is generated by
transceiver
The data interface is defined in such a way that all user
actions should take place on falling edge and is illustrated
Figure 7 and 8. The two figures illustrate the relationship
between DATACLK and DATAIXO in receive mode and
transmit mode.
MICRF600 will present data on rising edge and the
“USER” sample data on falling edge in receive mode.
When Sync_en = 1, it will enable the bit synchronizer in
receive mode. The bit synchronizer clock needs to be
DATAIXO
programmed,
see chapter
Bit synchronizer.
The
f BITRATE_CL K =
synchronized clock will be set out on pit DataClk.
In transmit mode, when Sync_en = 1, the clock signal on
pin DataClk is a programmed bit rate clock. Now the
transceiver controls the actual data rate. The data to be
transmitted will be sampled on rising edge of DataClk. The
micro controller can therefore use the negative edge to
change the data to be transmitted. The clock used for this
purpose, BitRate-clock, is programmed in the same way
as the modulator clock and the bit synchronizer clock:
f XCO
Refclk_K × 2 (7 -BITRATE_c lkS)
where:
f BITRATE_CLK : The clock frequency used to control the
bit rate, should be equal to the bit rate (bit rate of 20
kbit/sec requires a clock frequency of 20kHz)
f XCO : Crystal oscillator frequency
Refclk_K: 6 bit divider, values between 1 and 63
BitRate_clkS: Bit rate setting, values between 0 and
6
Data Interface
The MICRF600 interface can be divided in to two separate
interfaces, a “programming interface” and a “Data
interface”. The “programming interface” has a three wire
serial programmable interface and is described in chapter
Programming.
The “data interface” can be programmed to sync-/non-
synchronous mode. In synchronous mode the MICRF600
is defined as “Master” and provides a data clock that
allows users to utilize low cost micro controller reference
frequency.
DATACLK
Figure 7. Data interface in Receive Mode
The User presents data on falling edge and MICRF600 samples
on rising edge in transmit mode.
DATAIXO
DATACLK
Figure 8. Data interface in Transmit Mode
Receiver
The receiver is a zero intermediate frequency (IF) type in
order to make channel filtering possible with low-power
integrated low-pass filters. The receiver consists of a low
noise amplifier (LNA) that drives a quadrature mixer pair.
The mixer outputs feed two identical signal channels in
phase quadrature. Each channel includes a pre-amplifier,
a third order Sallen-Key RC lowpass filter from strong
adjacent channel signals and finally a limiter. The main
channel filter is a switched-capacitor implementation of a
six-pole elliptic lowpass filter. The elliptic filter minimizes
the total capacitance required for a given selectivity and
dynamic range. The cut-off frequency of the Sallen-Key
RC filter can be programmed to four different frequencies:
100kHz, 150kHz, 230kHz and 340kHz. The demodulator
demodulates the I and Q channel outputs and produces a
digital data output. If detects the relative phase of the I and
Q channel signal. If the I channel signal lags the Q
channel, the FSK tone frequency lies above the LO
frequency (data ‘1’). If the I channel leads the Q channel,
the FSK tone lies below the LO frequency (data ‘0’). The
output of the receiver is available on the DataIXO pin. A
RSSI circuit (receive signal strength indicator) indicates
the received signal level.
July 2006
14
M9999-082505
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